HD74HC173 Datasheet

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HD74HC173

4-bit D-type Register (with 3-state Outputs)

Description

The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the

device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the

output disable pins are in the logic high level.

The input disable allows the flip-flops to remain in their present states without having to disrupt the clock.

If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs,

forcing the flip-flops to remain in the same state. Clearing is enabled by taking the clear input to a logic

high level. The data outputs change state on the positive going edge of the clock.

Features

鈥?/div>

High Speed Operation: t

(Clock to Q) = 14 ns typ (C

= 50 pF)

High Output Current: Fanout of 10 LSTTL Loads

Wide Operating Voltage: V

= 2 to 6 V

Low Input Current: 1 碌A(chǔ) max

Low Quiescent Supply Current: I

(static) = 4 碌A(chǔ) max (Ta = 25擄C)

Function Table

Inputs

Data Enable

Clear

Clock

Data D

Output Q

Note: When either M or N (or both) is (are) high the output is disabled to the high-impedance state;

however sequential operation of the flip-flops is not affected.

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