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HD74HC165 Datasheet

  • HD74HC165

  • Parallel-load 8-bit Shift Register

  • 9頁

  • HITACHI

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HD74HC165
Parallel-load 8-bit Shift Register
Description
This 8-bit serial shift register shifts data from Q
A
to Q
H
when clocked. Parallel inputs to each stage are
enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary
output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with
the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of
the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the
parallel inputs is loaded directly into the register independent of the state of the clock.
Features
鈥?/div>
High Speed Operation: t
pd
(Clock to Q
H
) = 21 ns typ (C
L
= 50 pF)
鈥?/div>
High Output Current: Fanout of 10 LSTTL Loads
鈥?/div>
Wide Operating Voltage: V
CC
= 2 to 6 V
鈥?/div>
Low Input Current: 1 碌A(chǔ) max
鈥?/div>
Low Quiescent Supply Current: I
CC
(static) = 4 碌A(chǔ) max (Ta = 25擄C)
Function Table
Inputs
Parallel
Shift/Load
L
H
H
H
H
Clock Inhibit
X
L
L
L
H
X
Clock
X
L
Serial
X
X
H
L
X
A 路路路路路路 H
a 路路路路路路h
X
X
X
X
Internal outputs
Q
A
a
Q
A0
H
L
Q
A0
Q
B
b
Q
B0
Q
An
Q
An
Q
B0
Output
Q
H
h
Q
H0
Q
Gn
Q
Gn
Q
H0

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