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HD74CDCV857A Datasheet

  • HD74CDCV857A

  • Datasheet|ADE-205-693A|JUN.17.02|135K

  • 13頁(yè)

  • ETC

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HD74CDCV857A
2.5-V Phase-lock Loop Clock Driver
ADE-205-693A (Z)
Preliminary
Rev.1
Jun. 2002
Description
The HD74CDCV857A is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is
specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.
Features
鈥?/div>
Supports 60 MHz to 170 MHz operation range
鈥?/div>
Distributes one differential clock input pair to ten differential clock outputs pairs
鈥?/div>
Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM
specification
鈥?/div>
External feedback pins (FBIN,
FBIN)
are used to synchronize the outputs to the clock input
鈥?/div>
Supports 2.5V analog supply voltage (AV
CC
), and 2.5 V V
DDQ
鈥?/div>
No external RC network required
鈥?/div>
Sleep mode detection
鈥?/div>
48pin TSSOP (Thin Shrink Small Outline Package)
Function Table
Inputs
AVCC
PWRDWN
CLK
CLK
:
:
Outputs
Y
Y
FBOUT
FBOUT
:
L
H
Z
Z
L
H
Z
H
L
Z
Z
H
L
Z
:
:
:
:
:
:
:
PLL
Bypassed / off
*1
Bypassed / off
off
off
on
on
off
*1
GND
GND
X
X
2.5 V
2.5 V
2.5 V
H:
L:
X:
Z:
Notes:
H
H
L
L
H
H
X
L
H
H
L
L
H
H
L
L
H
H
L
Input clock frequency
60 to 170 MHz
鈫?/div>
0 MHz
:
:
:
:
:
:
:
L
H
Z
Z
L
H
Z
H
L
Z
Z
H
L
Z
High level
Low level
Don鈥檛 care
High impedance
1. Bypassed mode is used for Hitachi test mode.

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