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HD74CDCV852 Datasheet

  • HD74CDCV852

  • Datasheet|ADE-205-675C|DEC.26.02|81K

  • 81.88KB

  • 16頁

  • ETC

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HD74CDCV852
2.5 V PLL Clock Buffer for DDR Application
ADE-205-675C (Z)
Rev.3
Dec. 2002
Description
The HD74CDCV852 is a high-performance, low-skew, low-jitter, PLL clock buffer. It is specifically
designed for use with DDR (Double Data Rate) system board application.
Features
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Designed for DDR PC mother board clock buffering
Supports 60 MHz to 170 MHz operation range
Distributes 1 to 6 differential clock outputs pairs
Spread spectrum clock compatible
External feedback pin (FBIN) are used to synchronize the outputs to the clock input
Supports 2.5 V analog supply voltage (AVDD), and 2.5 V VDD
28pin SSOP package
Support output enable by I
2
C
TM
programming
Ordering Information
Package Type
SSOP-48 pin
Package Code
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Package
Abbreviation
SS
Taping
Abbreviation (Quantity)
EL (1,000 pcs / Reel)
Part Name
HD74CDCV852SSEL
Note: Please consult the sales office for the above package availability.
Note: I
2
C is a trademark of Philips Corporation.

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