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HD74CDC857 Datasheet

  • HD74CDC857

  • 3.3/2.5-V Phase-lock Loop Clock Driver

  • 12頁

  • HITACHI

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HD74CDC857
3.3/2.5-V Phase-lock Loop Clock Driver
ADE-205-222E (Z)
6th. Edition
July 1999
Description
The HD74CDC857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is
specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.
Features
鈥?/div>
Supports 100 MHz to 150 MHz operation range
*1
鈥?/div>
Distributes one differential clock input pair to ten differential clock outputs pairs
鈥?/div>
SSTL_2 (Stub Series Terminated Logic) differential inputs and LVCMOS reset (G) input
鈥?/div>
Supports spread spectrum clock
鈥?/div>
External feedback pins (FBIN,
FBIN)
are used to synchronize the outputs to the clock input
鈥?/div>
Supports both 3.3 V/2.5V analog supply voltage (AV
CC
), and 2.5 V V
DDQ
鈥?/div>
No external RC network required
鈥?/div>
Sleep mode detection
鈥?/div>
48pin TSSOP (Thin Shrink Small Outline Package)
Note: 1. 200 MHz (Max) ver. will be available by 4Q/鈥?9
Function Table
Inputs
G
L
L
H
H
X
H:
L:
Z:
X:
CLK
L
H
L
H
0 MHz
CLK
H
L
H
L
0 MHz
:
:
:
:
:
:
:
Outputs
Y
Z
Z
L
H
Z
Y
Z
Z
H
L
Z
FBOUT
Z
Z
L
H
Z
FBOUT
Z
Z
H
L
Z
:
:
:
:
:
off
off
run
run
off
:
PLL
High level
Low level
High impedance
Don鈥檛 care

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