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HD74ALVCH16831 Datasheet

  • HD74ALVCH16831

  • 1-to 4 Address Register / Driver with 3-state Outputs

  • 12頁

  • HITACHI

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HD74ALVCH16831
1-to 4 Address Register / Driver with 3-state Outputs
ADE-205-194 (Z)
Preliminary
1st. Edition
March 1998
Description
This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V V
CC
operation. The device is ideal
for use in applications in which a single address bus is driving four separate memory locations. The
HD74ALVCH16831 can be used as a buffer or a register, depending on the logic level of the select (SEL)
input. When
SEL
is logic high, the device is in the buffer mode. The outputs follow the inputs and are
controlled by the two output enable (OE) controls. Each
OE
controls two groups of nine outputs. When
SEL
is logic low, the device is in the register mode. The register is an edge triggered D-type flip flop. On
the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers.
OE
controls operate the same as in buffer mode. When
OE
is logic low, the outputs are in a normal logic
state (high or low logic level). When
OE
is logic high, the outputs are in the high impedance state. To
ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
driver.
SEL
and
OE
do not affect the internal operation of the flip flops. Old data can be retained or new
data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided
to hold unused or floating data inputs at a valid logic level.
Features
鈥?/div>
V
CC
= 2.3 V to 3.6 V
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
High output current 鹵24 mA (@V
CC
= 3.0 V)
鈥?/div>
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

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