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HD74ALVCH16721 Datasheet

  • HD74ALVCH16721

  • 3.3-V 20-bit Flip Flops with 3-state Outputs

  • 12頁

  • HITACHI

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HD74ALVCH16721
3.3-V 20-bit Flip Flops with 3-state Outputs
ADE-205-139B (Z)
3rd. Edition
December 1999
Description
The HD74ALVCH16721鈥檚 twenty flip flops are edge triggered D-type flip flops with qualified clock
storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs,
provided that the clock enable (CLKEN) input is low. If
CLKEN
is high, no data is stored. A buffered
output enable (OE) input can be used to place the twenty outputs in either a normal logic state (high or low
level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus
lines significantly. The high impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components. The output enable (OE) input does not affect the internal
operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the
high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid
logic level.
Features
鈥?/div>
V
CC
= 2.3 V to 3.6 V
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
High output current
鹵24
mA (@V
CC
= 3.0 V)
鈥?/div>
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

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