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HD74ALVCH16500 Datasheet

  • HD74ALVCH16500

  • 18-bit Universal Bus Transceivers with 3-state Outputs

  • 57.33KB

  • 13頁

  • HITACHI

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HD74ALVCH16500
18-bit Universal Bus Transceivers with 3-state Outputs
ADE-205-167A (Z)
2nd. Edition
December 1999
Description
Data flow in each direction is controlled by output enable (OEAB and
OEBA),
latch enable (LEAB and
LEBA), and clock (CLKAB and
CLKBA)
inputs. For A to B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is latched if
CLKAB
is held at a
high or low logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the high to low
transition of
CLKAB.
Output enable OEAB is active high. When OEAB is high, the B port outputs are
active. When OEAB is low, the B port outputs are in the high impedance state. Data flow for B to A is
similar to that of A to B but uses
OEBA,
LEBA, and
CLKBA.
The output enables are complementary
(OEAB is active high, and
OEBA
is active low). Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
Features
鈥?/div>
V
CC
= 2.3 V to 3.6 V
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
High output current
鹵24
mA (@V
CC
= 3.0 V)
鈥?/div>
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

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