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HD74ALVCH162500 Datasheet

  • HD74ALVCH162500

  • 18-bit Universal Bus Transceivers with 3-state Outputs

  • 13頁

  • HITACHI

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HD74ALVCH162500
18-bit Universal Bus Transceivers with 3-state Outputs
ADE-205-181 (Z)
Preliminary
1st. Edition
December 1996
Description
Data flow in each direction is controlled by output enable (OEAB and
OEBA),
latch enable (LEAB
and LEBA), and clock (CLKAB and
CLKBA)
inputs. For A to B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is latched if
CLKAB
is held at
a high or low logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the high to
low transition of
CLKAB.
Output enable OEAB is active high. When OEAB is high, the B port
outputs are active. When OEAB is low, the B port outputs are in the high impedance state. Data flow
for B to A is similar to that of A to B but uses
OEBA,
LEBA, and
CLKBA.
The output enables are
complementary (OEAB is active high, and
OEBA
is active low). Active bus hold circuitry is provided
to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up
to 12 mA, include 26
鈩?/div>
resistors to reduce overshoot and undershoot.
Features
鈥?/div>
V
CC
= 2.3 V to 3.6 V
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
High output current 鹵12 mA (@V
CC
= 3.0 V)
鈥?/div>
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
鈥?/div>
All outputs have equivalent 26
鈩?/div>
series resistors, so no external resistors are required.

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