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HD74ALVCH162270 Datasheet

  • HD74ALVCH162270

  • 12-bit to 24-bit Registered Bus Exchanger with 3-state Outpu...

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HD74ALVCH162270
12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
ADE-205-178A (Z)
2nd. Edition
March 1998
Description
The HD74ALVCH162270 is used in applications where data must be transferred from a narrow high speed
bus to a wide lower frequency bus. The device provides synchronous data exchange between the two ports.
Data is stored in the internal registers on the low to high transition of the clock (CLK) input when the
appropriate
CLKEN
inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data
transfer in the A to B direction, a two stage pipeline is provided in the A to 1B path, with a single storage
register in the A to 2B path. Proper control of the
CLKENA
inputs allows two sequential 12-bit words to
be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active low output
enables (OEA,
OEB).
The control terminals are registered to synchronize the bus direction changes with
CLK. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All
outputs, which are designed to sink up to 12 mA, include 26
鈩?/div>
resistors to reduce overshoot and
undershoot.
Features
鈥?/div>
V
CC
= 2.3 V to 3.6 V
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
High output current 鹵12 mA (@V
CC
= 3.0 V)
鈥?/div>
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
鈥?/div>
All outputs have equivalent 26
鈩?/div>
series resistors, so no external resistors are required.

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