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HD74ALVC162836 Datasheet

  • HD74ALVC162836

  • 20-bit Universal Bus Driver with 3-state Outputs

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HD74ALVC162836
20-bit Universal Bus Driver with 3-state Outputs
ADE-205-207 (Z)
Preliminary
1st. Edition
January 1998
Description
This 20-bit universal bus driver is designed for 2.3 V to 3.6 V V
CC
operation.
Data flow from A to Y is controlled by the output enable (OE) input. The device operates in the
transparent mode when the latch enable (LE) input is low. When
LE
is high, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE
is high, the A data is stored in the latch flip
flop on the low to high transition of CLK. When
OE
is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the
driver.
All outputs, which are designed to sink up to 12 mA, include 26
鈩?/div>
resistors to reduce overshoot and
undershoot.
Features
鈥?/div>
V
CC
= 2.3 V to 3.6 V
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
High output current
鹵12
mA (@V
CC
= 3.0 V)
鈥?/div>
All outputs have equivalent 26
鈩?/div>
series resistors, so no external resistors are required.

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