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HD74AC195 Datasheet

  • HD74AC195

  • 4-bit Parallel-Access Shift Register

  • 11頁

  • HITACHI

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HD74AC195
4-bit Parallel-Access Shift Register
Description
This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a
direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q
0
towards
Q
3
.
Parallel loading is accomplished by applying the four bits of data, and taking the
PE
Input low. The data is
loaded into the associated flip-flops and appears at the outputs after the positive transition of the CP input.
During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the
PE
input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to
perform as a J-K or toggle flip-flop as shown in the function table.
Features
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Shift Right and Parallel Load Capability
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J-K (D-Type) Inputs to First Stage
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Complement Output from Last Stage
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Asynchronous Master Reset
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Outputs Source/Sink 24 mA

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