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HCTS75D Datasheet

  • HCTS75D

  • Radiation Hardened Dual 2-Bit Bistable Transparent Latch

  • 9頁

  • INTERSIL   INTERSIL

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HCTS75MS
September 1995
Radiation Hardened
Dual 2-Bit Bistable Transparent Latch
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
Q0 1
D0 1
D1 1
E 2
VCC
D0 2
D1 2
Q1 2
1
2
3
4
5
6
7
8
16 1 Q0
15 1 Q1
14 1 Q1
13 1 E
12
11
GND
2 Q0
Features
鈥?3 Micron Radiation Hardened SOS CMOS
鈥?Total Dose 200K RAD (Si)
鈥?SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
鈥?Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
鈥?Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
鈥?Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Military Temperature Range: -55
o
C to +125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL ICs
鈥?DC Operating Voltage Range: 4.5V to 5.5V
鈥?LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
鈥?Input Current Levels Ii
鈮?/div>
5碌A(chǔ) at VOL, VOH
10 2 Q0
9
2 Q1
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
Q0 1
D0 1
D1 1
E 2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1 Q0
1 Q1
1 Q1
1 E
GND
2 Q0
2 Q0
2 Q1
Description
The Intersil HCTS75MS is a Radiation Hardened dual 2-bit
bistable transparent latch. Each of the two latches are controlled
by a separate enable input (E) which are active low. E low latches
the output state.
The HCTS75MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS75MS is supplied in a 16 lead Ceramic 鏗俛tpack
(K suf鏗亁) or a SBDIP Package (D suf鏗亁).
VCC
D0 2
D1 2
Q1 2
Functional Diagram
2(6)
D0
13(4)
E
LATCH 0
16(10
D
LE
Q
LE
1(11
Ordering Information
14(8
PART
NUMBER
HCTS75DMSR
TEMPERATURE
RANGE
-55
o
C to +125
o
C
-55
o
C
+125
o
C
SCREENING
LEVEL
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
PACKAGE
16 Lead SBDIP
3(7)
D1
5
12
VCC
GND
LE
D
LE
15(9
Q
LATCH 1
HCTS75KMSR
to
16 Lead Ceramic
Flatpack
16 Lead SBDIP
TRUTH TABLE
INPUTS
D
E
H
H
L
Q
L
H
Q0
OUTPUTS
Q
H
L
Q0
HCTS75D/
Sample
HCTS75K/
Sample
HCTS75HMSR
+25
o
C
+25
o
C
+25
o
C
Sample
16 Lead Ceramic
Flatpack
Die
L
H
Die
X
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
Spec Number
File Number
470
518625
3189.1

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