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HCTS646D Datasheet

  • HCTS646D

  • Radiation Hardened Octal Bus Transceiver/Register, Three-Sta...

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  • INTERSIL   INTERSIL

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HCTS646MS
August 1995
Radiation Hardened
Octal Bus Transceiver/Register, Three-State
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
CAB 1
SAB 2
DIR 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 VCC
23 CBA
22 SBA
21 OE
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
Features
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3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Cosmic Ray Upset Rate 2 x 10
-9
Errors/Bit Day
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Signi鏗乧ant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2
Input Current Levels Ii
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5碌A(chǔ) at VOL, VOH
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Description
The Intersil HCTS646MS is a Radiation Hardened Three-
State Octal Bus Tranceiver/Register with Non-Inverting
outputs. This device is a bus transceiver with D-type 鏗俰p-鏗俹ps
which act as internal storage registers. Data on the A bus or
the B bus can be clocked into the registers on a High-to-Low
transition of either CAB ro CBA clock inputs. Output enable
(OE) and Direction (DIR) inputs control the transceiver func-
tions. Data present at the high impedance output can be
stored in either register or both but only one of the two buses
can be enabled as outputs at any one time. The select con-
trols (SAB and SBA) can multiplex stored and transparent
(real time) data. The direction control determines which data
bus will receive data when the OE pin is LOW. In the high
impedance mode (OE high), A data can be stored in one reg-
ister and B data in the other register. Data at the A or B termi-
nals can be clocked into the storage 鏗俰p-鏗俹ps at any time.
The HCTS646MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS646MS is supplied in a 24 lead Ceramic 鏗俛tpack
(K suf鏗亁) or a SBDIP Package (D suf鏗亁).
24 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
CAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
CBA
SBA
OE
B0
B1
B2
B3
B4
B5
B6
B7
Ordering Information
PART NUMBER
HCTS646DMSR
HCTS646KMSR
HCTS646D/Sample
HCTS646K/Sample
HCTS646HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
24 Lead SBDIP
24 Lead Ceramic Flatpack
24 Lead SBDIP
24 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
Spec Number
File Number
706
518628
3074.1

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