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HCTS373D Datasheet

  • HCTS373D

  • Radiation Hardened Octal Transparent Latch, Three-State

  • 280.83KB

  • 11頁

  • INTERSIL   INTERSIL

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HCTS373MS
August 1995
Radiation Hardened
Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
Features
鈥?3 Micron Radiation Hardened CMOS SOS
鈥?Total Dose 200K RAD (Si)
鈥?SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
鈥?Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-
Day (Typ)
鈥?Dose Rate Survivability: >1 x 10
鈥?Dose Rate Upset >10
10
RAD
12
RAD (Si)/s
(Si)/s 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
鈥?Military Temperature Range: -55
o
C to +125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL ICs
鈥?DC Operating Voltage Range: 4.5V to 5.5V
鈥?LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
鈥?Input Current Levels Ii
鈮?/div>
5碌A at VOL, VOH
GND 10
Description
The Intersil HCTS373MS is a Radiation Hardened octal transpar-
ent three-state latch with an active-low output enable. The out-
puts are transparent to the inputs when the Latch Enable (LE) is
HIGH. When the Latch Enable (LE) goes LOW, the data is
latched. The Output Enable (OE) controls the three-state outputs.
When the Output Enable (OE) is HIGH, the outputs are in the
high impedance state. The latch operation is independent of the
state of the Output Enable.
The HCTS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS373MS is supplied in a 20 lead Ceramic 鏗俛tpack (K
suf鏗亁) or a SBDIP Package (D suf鏗亁).
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
Ordering Information
PART NUMBER
HCTS373DMSR
HCTS373KMSR
HCTS373D/Sample
HCTS373K/Sample
HCTS373HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
DB NA
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
Spec Number
File Number
638
518636
2131.2

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