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HCTS191KMSR Datasheet

  • HCTS191KMSR

  • Radiation Hardened Synchronous 4-Bit Up/Down Counter

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  • INTERSIL   INTERSIL

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HCTS191MS
September 1995
Radiation Hardened
Synchronous 4-Bit Up/Down Counter
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835 CDIP2-T16
TOP VIEW
P1
Q1
Q0
CE
U/D
Q2
Q3
GND
1
2
3
4
5
6
7
8
16 VCC
15 P0
14 CP
13 RC
12 TC
11 PL
10 P2
9 P3
Features
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3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-
Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset: >10
10
RAD (Si)/s 20ns Pulse
Cosmic Ray Upset Immunity 2 x 10
-9
Errors/Bit Day
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Standard Outputs - 10 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Signi鏗乧ant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
鈮?/div>
5碌A(chǔ) @ VOL, VOH
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP4-F16
TOP VIEW
P1
Q1
Q0
CE
U/D
Q2
Q3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
P0
CP
RC
TC
PL
P2
P3
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Description
The Intersil HCTS191MS is a Radiation Hardened asynchro-
nously presettable 4 bit binary up/down synchronous counter.
Presetting the counter to the number on the preset data inputs
(P0 - P3) is accomplished by a low asynchronous parallel load
input (PL). Counting occurs when PL is high, Count Enable (CE)
is low, and the Up/Down (U/D) input is either low for up-counting
or high for down-counting. The counter is incremented or decre-
mented synchronously with the low-to-high transition of the clock.
When an over鏗俹w or under鏗俹w of the counter occurs, the
Terminal Count output (TC), which is low during counting, goes
high and remains high for one clock cycle. This output can be
used for look-ahead carry in high speed cascading. The TC
output also initiates the Ripple Clock output (RC) which, normally
high, goes low and remains low for the low-level portion of the
clock pulse. These counter can be cascaded using the Ripple
Carry output.
The HCTS191MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS191MS is supplied in a 16 lead Ceramic 鏗俛tpack
(K suf鏗亁) or a SBDIP Package (D suf鏗亁).
TRUTH TABLE
FUNCTION
Count Up
Count Down
Asynchronous Preset
No Change
PL
H
H
L
H
CE
L
L
X
H
U/D
L
H
X
X
X
X
CP
H = High Level, L = Low Level, X = Immaterial
= Transition from low to high
NOTE: U/D or CE should be changed only when CLOCK (CP)
is high.
Ordering Information
PART NUMBER
HCTS191DMSR
HCTS191KMSR
HCTS191D/Sample
HCTS191K/Sample
HCTS191HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
DB NA
16 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
Spec Number
File Number
580
518621
2250.2

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