HCS245MS
December 1992
Radiation Hardened
Octal Bus Transceiver, Three-State, Non-Inverting
Pinouts
20 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T20, LEAD FINISH C
TOP VIEW
DIR
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 VCC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
Features
鈥?3 Micron Radiation Hardened CMOS SOS
鈥?Total Dose 200K or 1 Mega-RAD(Si)
鈥?Latch-Up Free Under Any Conditions
鈥?Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
鈥?Military Temperature Range: -55
o
C to +125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL ICs
鈥?DC Operating Voltage Range: 4.5V to 5.5V
鈥?LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
鈥?Input Current Levels Ii
鈮?/div>
5碌A at VOL, VOH
GND 10
Description
The Intersil HCS245MS is a Radiation Hardened Non-Invert-
ing Octal Bidirectional Bus Transceiver, Three-State,
intended for two-way asynchronous communication between
data busses. The HCS245MS allows data transmission from
the A bus to the B bus or from the B bus to the A bus. The
logic level at the direction input (DIR) determines the data
direction. The output enable input (OE) puts the I/O port in
the high-impedance state when high.
The HCS245MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS245MS is supplied in a 20 lead Weld Seal Ceramic
鏗俛tpack (K suf鏗亁) or a Weld Seal Ceramic Dual-In-Line
Package (D suf鏗亁).
20 PIN CERAMIC FLAT PACK
MIL-STD-1835 DESIGNATOR CDFP4-F20, LEAD FINISH C
TOP VIEW
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
OE
B0
B1
B2
B3
B4
B5
B6
B7
Truth Table
CONTROL
INPUTS
OE
L
L
H
DIR
L
H
X
OPERATION
B Data to A Bus
A Data to B Bus
Isolation
Functional Diagram
ONE OF 8 TRANSCEIVERS
A DATA
9
B DATA
11
(18, 17, 16, 15,
14, 13, 12)
TO OTHER
7 BUFFERS
(2, 3, 4, 5,
6, 7, 8)
H = High Voltage Level, L = Low Voltage Level,
X = Immaterial
To prevent excess currents in the High-Z (Isolation)
modes, all I/O terminals should be terminated with 10k鈩?/div>
to 1M鈩?resistors.
DIR
1
OUTPUT
ENABLE 19
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
File Number
2468.1
7-475
INTERSIL
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