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HCS11MS Datasheet

  • HCS11MS

  • Radiation Hardened Triple 3-Input AND Gate

  • 6頁

  • INTERSIL   INTERSIL

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HCS11MS
November 1994
Radiation Hardened
Triple 3-Input AND Gate
Pinouts
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
A2 3
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
Features
鈥?3 Micron Radiation Hardened SOS CMOS
鈥?Total Dose 200K or 1 Mega-RAD(Si)
鈥?Dose Rate Upset >10
10
RAD(Si)/s 20ns Pulse
鈥?Cosmic Ray Upset Immunity < 2 x 10
-9
Errors/Gate Day
(Typ)
鈥?Latch-Up Free Under Any Conditions
鈥?Military Temperature Range: -55
o
C
to
+125
o
C
B2 4
C2 5
Y2 6
GND 7
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL ICs
鈥?DC Operating Voltage Range: 4.5V to 5.5V
鈥?Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
鈥?Input Current Levels Ii
鈮?/div>
5碌A(chǔ) at VOL, VOH
Description
The Intersil HCS11MS is a Radiation Hardened Triple 3-
Input AND Gate. A high on all inputs forces the output to a
High state.
The HCS11MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS11MS is supplied in a 14 lead Weld Seal Ceramic
鏗俛tpack (K suf鏗亁) or a Weld Seal Ceramic Dual-In-Line
Package (D suf鏗亁).
14 PIN CERAMIC FLAT PACK
MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
A2
B2
C2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
C1
Y1
C3
B3
A3
Y3
Truth Table
INPUTS
An
L
L
L
L
H
H
H
H
Bn
L
L
H
H
L
L
H
H
Cn
L
H
L
H
L
H
L
H
OUTPUTS
Yn
L
L
L
L
L
L
L
H
Functional Diagram
(1, 3, 9)
An
(2, 4, 10)
Bn
(12, 6, 8)
Yn
(13, 5, 11)
Cn
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
File Number
3048
7-135

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