鈥?/div>
Compact SO8 package
Very high speed-10 MBit/s
Superior CMR-10 kV/碌s
Fan-out of 8 over -40擄C to +85擄C
Logic gate output
Strobable output
Wired OR-open collector
U.L. recognized (File # E90700)
PACKAGE DIMENSIONS
0.164 (4.16)
0.144 (3.66)
SEATING PLANE
Pin 1
APPLICATIONS
鈥?Ground loop elimination
鈥?LSTTL to TTL, LSTTL or
5-volt CMOS
鈥?Line receiver, data transmission
鈥?Data multiplexing
鈥?Switching power supplies
鈥?Pulse transformer replacement
鈥?Computer-peripheral interface
N/C 1
8 V
CC
0.202 (5.13)
0.182 (4.63)
0.019 (0.48)
0.010 (0.25)
0.006 (0.16)
+ 2
V
F
_
3
7 V
E
0.143 (3.63)
0.123 (3.13)
6 V
O
0.021 (0.53)
0.011 (0.28)
0.008 (0.20)
0.003 (0.08)
0.050 (1.27)
TYP
0.244 (6.19)
0.224 (5.69)
N/C 4
5 GND
Lead Coplanarity : 0.004 (0.10) MAX
Single-channel
circuit drawing
NOTE
All dimensions are in inches (millimeters)
TRUTH TABLE
(Positive Logic)
Input
H
L
H
L
H
L
Enable
H
H
L
L
NC
NC
Output
L
H
H
H
L
H
A 0.1 碌F bypass capacitor must be connected between pins 8 and 5. (See note 1)
漏 2003 Fairchild Semiconductor Corporation
Page 1 of 12
4/10/03