HCF4029B
PRESETTABLE UP/DOWN COUNTER
BINARY OR BCD DECADE
s
s
s
s
s
s
s
s
s
s
MEDIUM SPEED OPERATION : 8MHz (Typ.)
at C
L
= 50pF and V
DD
- V
SS
= 10V
MULTI-PACKAGE PARALLEL CLOCKING
FOR SYNCHRONOUS HIGH SPEED
OUTPUT RESPONSE OR RIPPLE
CLOCKING FOR SLOW CLOCK INPUT RISE
AND FALL TIMES
"PRESET ENABLE" AND INDIVIDUAL "JAM"
INPUTS PROVIDED
BINARY OR DECADE UP/DOWN
COUNTING
BCD OUTPUTS IN DECADE MODE
QUIESCENT CURRENT SPECIF. UP TO 20V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25擄C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DIP
SOP
ORDER CODES
PACKAGE
DIP
SOP
TUBE
HCF4029BEY
HCF4029BM1
T&R
HCF4029M013TR
DESCRIPTION
HCF4029B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4029B consists of a four stage binary or
BCD-decade up/down counter with provisions for
look ahead carry in both counting modes. The
PIN CONNECTION
inputs consist of a single CLOCK, CARRY IN
(CLOCK ENABLE), BINARY/DECADE, UP/
DOWN, PRESET ENABLE, and four individual
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT
signal are provided as outputs. A high PRESET
ENABLE signal allows information on the JAM
INPUTS to preset the counter to any state
asynchronously with the clock. A low on each JAM
line, when the PRESET-ENABLE signal is high,
resets the counter to its zero count. The counter
advances one count at the positive transition of
the clock when the CARRY-IN and PRESET
ENABLE signals are low. Advancement is
inhibited when the CARRY-IN or PRESET
ENABLE signals are high. The CARRY-OUT
September 2002
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