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HCF40105BC1 Datasheet

  • HCF40105BC1

  • FIFO REGISTER

  • 12頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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HCC40105B
HCF40105B
FIFO REGISTER
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INDEPENDENT ASYNCHRONOUS INPUTS
AND OUTPUTS
3-STATE OUTPUTS
EXPANDABLE IN EITHER DIRECTION
STATUS INDICATORS ON INPUT AND OUT-
PUT
RESET CAPABILITY
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25擄C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N
o
13A, 鈥漇TANDARD
SPECIFICATIONS FOR DESCRIPTION OF 鈥滲鈥?/div>
SERIES CMOS DEVICES鈥?/div>
READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data
stack (the output end), all data entered later will auto-
matically propagate (ripple) toward the output.
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC40105BF
HCF40105BEY
HCF40105BC1
DESCRIPTION
The
HCC40105B
(extended temperature range) and
HCF40105B
(intermediate temperature range) are
monolithic integrated circuits, available in 16-lead dual
in-line plastic or ceramic package.
The
HCC/HCF40105B
is a low-power first-in-first-out
(FIFO) 鈥漞lastic鈥?storage register that can store 16 4-bit
words. It is capable of handling input and output data
at different shifting rates. This feature makes it particu-
larly useful as a buffer between asynchronous sys-
tems. Each word position in the register is clocked by
a control flip-flop, which stores a marker bit. A 鈥?鈥?sig-
nifies that the position鈥檚 data is filled and a 鈥?鈥?denotes
a vacancy in that position. The control flip-flop detects
the state of the preceding flip-flop and communicates
its own status to the succeeding flip-flop. When a con-
trol flip-flop is in the 鈥?鈥?state and sees a 鈥?鈥?in the
preceding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches
into its own four data latches and resets the preceding
flip-flop to 鈥?鈥? The first and last control flip-flops have
buffered outputs. Since all empty locations 鈥漛ubble鈥?/div>
automatically to the input end, and all valid data ripple
through to the output end, the status of the first control
flip-flop (DATA-IN READY) indicates if the FIFO is full,
and the status of the last flip-flop (DATA-OUT
June 1989
PIN CONNECTIONS
1/12

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