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HCF40103B Datasheet

  • HCF40103B

  • 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

  • 13頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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上傳產(chǎn)品規(guī)格書

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HCC/HCF40102B
HCC/HCF40103B
8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
40102B 2-DECADE BCD TYPE
40103B 8-BIT BINARY TYPE
SYNCHRONOUS
OR
ASYNCHRONOUS
PRESET
MEDIUM-SPEED OPERATION : f
CL
= 3.6MHz
(TYP.) @ V
DD
= 10V
CASCADABLE
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100 nA AT 18V AND 25擄C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
o
TATIVE STANDARD N . 13 A, 鈥漇TANDARD
SPECIFICATIONS FOR DESCRIPTION OF 鈥滲鈥?/div>
SERIES CMOS DEVICES鈥?/div>
.
.
.
.
.
.
.
.
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC401XXBF
HCF401XXBEY
HCF401XXBC1
DESCRIPTION
The
HCC40102B, HCC40103B,
(extended tempera-
ture range) and the
HCF40102B, HCF40103B
(inter-
mediate temperature range) are monolithic integrated
circuits, available in 16-lead dual in-line plastic or ce-
ramic package. The
HCC/HCF40102B,
and
HCC/HCF40103B
consist of an 8-stage synchronous
down counter with a single output which is active when
the internal count is zero. The
HCC/HCF40102B
is
configured as two cascaded 4-bit BCD counters, and
the
HCC/HCF40103B
contains a single 8-bit binary
counter. Each type has control inputs for enabling or
disabling the clock, for clearing the counter to its
maximum count, and for presetting the counter
either synchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT out-
put are active-low logic. In normal operation, the
counter is decremented by one count on each posi-
tive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETEC
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low, data at the
JAM input is clocked into the counter on the next
positive clock transition regardless of the state of the
CI/CE input. When the ASYNCHRONOUS
PRESET-ENABLE (APE) input is low, data at the
June 1989
PIN CONNECTIONS
1/13

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