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HCC4042B Datasheet

  • HCC4042B

  • QUAD CLOCKED ”D” LATCH

  • 13頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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HCC/HCF4042B
QUAD CLOCKED 鈥滵鈥?LATCH
.
.
.
.
.
.
.
.
.
.
CLOCK POLARITY CONTROL
Q AND Q OUTPUTS
COMMON CLOCK
LOW POWER TTL COMPATIBLE
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25擄C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N擄 13A, 鈥漇TANDARD SPE-
CIFICATIONS FOR DESCRIPTION OF 鈥滲鈥?/div>
SERIES CMOS DEVICES鈥?/div>
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Plastic Chip Carrier)
ORDER CODES :
HCC4042BF
HCF4042BM1
HCF4042BEY
HCF4042BC1
PIN CONNECTIONS
DESCRIPTION
The
HCC4042B
(extended temperature range) and
HCF4042B
(intermediate temperature range) are
monolithic integrated circuit, available in 16-lead
dual in-line plastic or ceramic package and plastic
micro package.
The
HCC/HCF4042B
types contain four latch cir-
cuits, each strobed by a common clock. Com-
plementary buffered outputs are available from
each circuit. The impedance of the n- and p-channel
output devices is balanced and all outputs are elec-
trically identical.
Information present at the data input is transferred
to outputs Q and Q during the CLOCK level which
is programmed by the POLARITY input. For PO-
LARITY = 0 the transfer occurs during the 0 CLOCK
level and for POLARITY = 1 the transfer occurs dur-
ing the 1 CLOCK level. The outputs follow the data
input providing the CLOCK and POLARITY levels
defined above are present. When a CLOCK transi-
tion occurs (positive for POLARITY = 0 and negative
for POLARITY = 1) the information present at the
input during the CLOCK transition is retained at the
outputs until an opposite CLOCK transition occurs.
June 1989
1/13

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