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HCC40104B Datasheet

  • HCC40104B

  • 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

  • 12頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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HCC/HCF40104B
HCC/HCF40194B
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
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MEDIUM-SPEED OPERATION : f
CL
= 9MHz
(typ.) @ V
DD
= 10V
FULLY STATIC OPERATION
SYNCHRONOUS PARALLEL OR SERIAL
OPERATION
THREE-STATE OUTPUTS (HCC/HCF40104B)
ASYNCHRONOUS
MASTER
RESET
(HCC/HCF40194B)
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT AT 20V FOR HCC DE-
VICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25擄C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N擄 13A, 鈥漇TANDARD SPE-
CIFICATIONS FOR DESCRIPTION OF 鈥滲鈥?/div>
SERIES CMOS DEVICES鈥?/div>
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Plastic Chip Carrier )
ORDER CODES :
HCC401XXBF
HCF401XXBEY
HCF401XXBC1
DESCRIPTION
The
HCC40104B, HCC40194B,
(extended tem-
perature range) and the
HCC40104B, HCF40194B
(intermediate temperature range) are monolithic in-
tegrated circuits, available in 16-lead dual in-line
plastic or ceramic package and plastic micro pack-
age. The
HCC/HCF 40104B
is a universal shift reg-
ister featuring parallel inputs, parallel outputs, SHIFT
RIGHT and SHIFT LEFT serial inputs, and a high-im-
pedance third output state allowing the device to be
used in bus-organized systems. In the parallel-load
mode (S0 and S1 are high), data is loaded into the
associated flip-flop and appears at the output after
the positive transition of the CLOCK input. During
loading, serial data flow is inhibited. Shift-right and
shift-left are accomplished synchronously on the
positive clock edge with serial data entered at the
SHIFT RIGHT and SHIFT LEFT serial inputs, re-
spectively. Clearing the register is accomplished by
setting both mode controls low and clocking the reg-
ister. When the output enable input is low, all outputs
assume the high impedance state. The
HCC/HCF40194B
is a universal shift register featur-
ing parallel inputs, parallel outputs SHIFT RIGHT and
SHIFT LEFT serial inputs, and a direct overriding
clear input. In the parallel-load mode (S0 and S1 are
high), data is loaded into the associated flip-flop and
June 1989
PIN CONNECTIONS
40104B
40194B
1/12

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