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HC74 Datasheet

  • HC74

  • Dual D Flip-Flop with Set and Reset(High-Performance Silicon...

  • 5頁

  • SLS

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SL74HC74
Dual D Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The SL74HC74 is identical in pinout to the LS/ALS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two D flip-flops with individual Set, Reset,
and Clock inputs. Information at a D-input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip-flop. The Set
and Reset inputs are asynchronous.
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
鈥?/div>
Operating Voltage Range: 2.0 to 6.0 V
鈥?/div>
Low Input Current: 1.0
碌A(chǔ)
鈥?/div>
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC74N Plastic
SL74HC74D SOIC
T
A
= -55擄 to 125擄 C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Set
L
H
L
PIN 14 =V
CC
PIN 7 = GND
H
H
H
H
H
Reset
H
L
L
H
H
H
H
H
L
H
Clock
X
X
X
Data
X
X
X
H
L
X
X
X
Outputs
Q
H
L
H
*
H
L
Q
L
H
H
*
L
H
No Change
No Change
No Change
*Both outputs will remain high as long as Set
and Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
X = don鈥檛 care
System Logic
Semiconductor
SLS

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