H鈥?/div>
description/ordering information
The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and
storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial
output for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
ORDERING INFORMATION
TA
PDIP 鈭?E
SOIC 鈭?DW
PACKAGE鈥?/div>
Tube of 25
Tube of 40
Reel of 2000
Tube of 40
鈭?5 C 125擄C
鈭?5擄C to 125 C
SOIC 鈭?M
SOP 鈭?NS
SSOP 鈭?SM
Reel of 2500
Reel of 250
Reel of 2000
Tube of 80
Reel of 2000
ORDERABLE
PART NUMBER
CD74HC595E
CD74HC595DW
CD74HC595DWR
CD74HC595M
CD74HC595M96
CD74HC595MT
CD74HC595NSR
CD74HC595SM
CD74HC595SM96
HC595M
HJ595
HC595M
HC595M
TOP-SIDE
MARKING
CD74HC595E
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2004, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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