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HC573 Datasheet

  • HC573

  • Octal 3-State Noninverting Transparent Latch(High-Performanc...

  • 5頁(yè)

  • SLS

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SL74HC573
Octal 3-State Noninverting Transparent Latch
High-Performance Silicon-Gate CMOS
The SL74HC573 is identical in pinout to the LS/ALS573. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
鈥?/div>
Operating Voltage Range: 2.0 to 6.0 V
鈥?/div>
Low Input Current: 1.0
碌A(chǔ)
鈥?/div>
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC573N Plastic
SL74HC573D SOIC
T
A
= -55擄 to 125擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output
Enable
L
L
L
H
Latch
Enable
H
H
L
X
D
H
L
X
X
Output
Q
H
L
no change
Z
X = don鈥檛 care
Z = high impedance
SLS
System Logic
Semiconductor

HC573相關(guān)型號(hào)PDF文件下載

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  • 英文版
    Octal 3-State Noninverting Transparent Latch(High-Performanc...
    SLS
  • 英文版
    Octal 3-State Noninverting Transparent Latch(High-Performanc...
    SLS [Syste...
  • 英文版
    OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
    TI [Texas ...

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