Data sheet acquired from Harris Semiconductor
SCHS143
CD74HC125,
CD74HCT125
High Speed CMOS Logic
Quad Buffer, Three-State
Description
The Harris CD74HC125 and CD74HCT125 contain 4 inde-
pendent three-state buffers, each having its own output
enable input, which when 鈥淗IGH鈥?puts the output in the high
impedance state
November 1997
Features
鈥?Three-State Outputs
鈥?Separate Output Enable Inputs
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A at V
OL
, V
OH
[ /Title
(CD74
HC125
,
CD74
HCT12
5)
/Sub-
ject
(High
Speed
CMOS
Logic
Quad
Buffer,
Three-
State)
Ordering Information
PART NUMBER
CD74HC125E
CD74HCT125E
CD74HC125M
CD74HCT125M
NOTES:
1. When ordering, use the entire part number. Add the suf鏗亁 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld PDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
PKG.
NO.
E14.3
E14.3
M14.15
M14.15
Pinout
CD74HC125, CD74HCT125
(PDIP, SOIC)
TOP VIEW
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 V
CC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1997
File Number
1771.1
1
1
2
3
4
5
6
7
