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H8250 Datasheet

  • H8250

  • Universal Asynchronous Receiver/Transmitter

  • 7頁

  • ETC

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H8250 Megafunction
Universal Asynchronous
Receiver/Transmitter
General Description
The H8250 is a standard UART providing 100%
software compatibility with the popular Intel 8250
device. It performs serial-to-parallel conversion on
data originating from modems or other serial
devices, and performs parallel-to-serial
conversion on data from a CPU to these devices.
Developed for easy reuse in Altera FPGA
applications, the H8250 is available optimized for
several device families with competitive utilization
and performance characteristics.
Features
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Capable of running all existing 8250 software
Adds or deletes standard asynchronous
communication bits (start, stop and parity) to
or from the serial data
Independently controlled transmit, receive,
line status and data set interrupts
Programmable baud generator divides any
input clock by 1 to (2
16
- 1) and generates the
16 x clock
Independent receiver clock input
Modem control functions (CTSn, RTSn, DSRn,
DTRn, RIn, and DCDn)
Fully programmable serial interface
characteristics:
o
o
o
o
5, 6, 7, or 8 bit characters
Even, odd, or no-parity bit generation and
detection
1, 1錕?frac12;, or 2 stop bit generation
Baud generation
Symbol
A(2:0)
CS
RD
WR
MR
CLK
DIN(7:0)
RCLK
SIN
CTSn
DSRn
DCDn
RIn
H8250
DOUT(7:0)
SOUT
DDIS
RTSn
DTRn
OUT1n
OUT2n
INTR
BOUDOUTn
RXRDY
TXRDY
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False start bit detection
Complete status register
Internal diagnostic capabilities: loopback
controls for communications link fault isolation
Full prioritized interrupt system controls
Applications
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Serial or modem computer interface
Serial interface within modems and other devices
CAST, Inc.
June 2002
Page 1

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