GTLP8T306 8-Bit LVTTL/GTLP Bus Transceiver
September 1997
Revised April 2000
GTLP8T306
8-Bit LVTTL/GTLP Bus Transceiver
General Description
The GTLP8T306 is an 8-bit bus transceiver that provides
LVTTL to GTLP signal level translation. The device pro-
vides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTLP
logic levels. High speed backplane operation is a direct
result of GTLP鈥檚 reduced output swing (<1V), reduced input
threshold levels and output edge rate control. The edge
rate control minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild鈥檚 GTLP has internal output edge-rate control and
is process, voltage, and temperature (PVT) compensated.
Its function is similar to BTL and GTL but with different out-
put levels and receiver thresholds. The GTLP output LOW
level is typically less than 0.5V, the output HIGH level is
1.5V and the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTL/GTLP and LVTTL
logic levels
s
Output Edge Rate Control to minimize noise on the
GTLP port
s
Power up/down/off high impedance for live insertion
s
Standard 245 function
s
CMOS technology for low power dissipation
s
5V tolerant inputs and outputs on the A-Port
s
Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs
s
LVTTL compatible driver and control inputs
s
Flow through pinout optimizes PCB layout
s
Open drain on GTLP to support wired-or connection
s
A-Port source/sink
鈭?4
mA/+24 mA
s
B-Port sink 50 mA
s
Recommended Operating Temperature
鈭?0擄C
to
+85擄C
Ordering Code:
Order Number
GTLP8T306MTC
Package Number
MTC24
Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
Connection Diagram
漏 2000 Fairchild Semiconductor Corporation
DS500051
www.fairchildsemi.com