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GTLP6C816 Datasheet

  • GTLP6C816

  • GTLP-to-TTL 1:6 Clock Driver

  • 7頁

  • FAIRCHILD

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GTLP6C816 GTLP-to-TTL 1:6 Clock Driver
June 1998
Revised October 1998
GTLP6C816
GTLP-to-TTL 1:6 Clock Driver
General Description
The GTLP6C816 is a clock driver that provides TTL to
GTLP signal level translation (and vice versa). The device
provides a high speed interface between cards operating at
TTL logic levels and a backplane operating at GTLP logic
levels. High speed backplane operation is a direct result of
GTLP鈥檚 reduced output swing (<1V), reduced input thresh-
old levels and output edge rate control. The edge rate con-
trol minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild鈥檚 GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Interface between TTL and GTLP logic levels
s
Edge Rate Control to minimize noise on the GTLP port
s
Power up/down high impedance for live insertion
s
1:6 fanout clock driver for TTL port
s
1:2 fanout clock driver for GTLP port
s
TTL compatible driver and control inputs
s
Flow through pinout optimizes PCB layout
s
Open drain on GTLP to support wired-or connection
s
Recommended Operating Temperature
鈭?0擄C
to
+85擄C
Ordering Code:
Order Number
GTLP6C816MTC
Package Number
MTC24
Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Descriptions
Pin Names
Description
TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively)
OEB
OEA
V
CCT
.GNDT
V
CC
GNDG
V
REF
OA0鈥揙A5
OB0鈥揙B1
Output Enable (Active LOW)
GTLP Port (TTL Levels)
Output Enable (Active LOW)
TTL Port (TTL Levels)
TTL Output Supplies (5V)
Internal Circuitry V
CC
(5V)
OBn GTLP Output Grounds
Voltage Reference Input
TTL Buffered Clock Outputs
GTLP Buffered Clock Outputs
Connection Diagram
漏 1998 Fairchild Semiconductor Corporation
DS500129.prf
www.fairchildsemi.com

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