Logic Block Diagram
OEB
OB0
TTLIN
OEA
OA0
OA1
OB1
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GTLP6C816
GTLP-to-TTL 1:6 Clock Driver
Features
聲 Bidirectional interface between GTLP and TTL
logic levels
聲 Designed with Edge Rate Control Circuit to
reduce output noise on the GTLP port
聲 Power up/down high impedance for live insertion
聲 1:6 fanout clock driver for TTL port
聲 Lower Drive (12mA) on TTL Port to reduce noise
聲 1:2 fanout clock driver for GTLP port
聲 TTL compatible driver and control inputs
聲 Flow -through architecture optimizes PCB layout
聲 Open drain on GTLP to support wired-or connection
聲 Operating Temperature: 聳40擄C to +85擄C
聲 Package:
聳 24-Pin 173 mil wide plastic TSSOP (L24)
Product Description
Pericom Semiconductor聮s GTLP series of logic circuits are produced
using the Company聮s advanced 0.5 micron CMOS technology,
achieving industry leading performance.
The GTLP6C816 is a clock driver that provides TTL to GTLP signal
level translation (and vice versa). The device provides a high-speed
interface between cards operating at TTL logic levels and a backplane
operating at GTLP logic levels. High-speed backplane operation is
a direct result of GTLP聮s reduced output swing (<1V), reduced input
threshold levels, and output edge-rate control which minimizes bus
settling times.
Pericom聮s GTLP has internal edge-rate control. Its function is similar
to BTL or GTL but with different output levels and receiver threshold.
GTLP output low voltage is typically less than 0.5V, the output level
HIGH is 1.5V and the receiver threshold is 1.0V.
PinConfiguration
GTLP
Ports
TTL
Ports
OA5
GTLPIN
TTLIN
OA0
GNDT
OA1
V
CCT
OA2
GNDT
OA3
V
CCT
OA4
GNDT
OA5
24
1
23
2
22
3
21
4
20
5
24-Pin
19
6
L
18
7
17
8
9
16
10
15
11
14
12
13
GNDT
OEB
OB0
GNDG
V
REF
GNDG
V
CC
OB1
GNDG
GTLPIN
OEA
GNDT
1
PS8426A
03/15/00
1
2
3
4
5
6
