GTLP6C816A GTLP/LVTTL 1:6 Clock Driver
August 1998
Revised December 2000
GTLP6C816A
GTLP/LVTTL 1:6 Clock Driver
General Description
The GTLP6C816A is a clock driver that provides LVTTL to
GTLP signal level translation (and vice versa). The device
provides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTL(P)
logic levels. High speed backplane operation is a direct
result of GTLP鈥檚 reduced output swing (
<
1V), reduced input
threshold levels and output edge rate control. The edge
rate control minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild鈥檚 GTL(P) has internal edge-rate control and is
process, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Interface between LVTTL and GTLP logic levels
s
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
A Port source/sink
鈭?/div>
24mA/
+
24mA
s
B Port sink
+
50mA
s
1:6 fanout clock driver for TTL port
s
1:2 fanout clock driver for GTLP port
s
Low voltage version of GTLP6C816
Ordering Code:
Order Number
GTLP6C816AMTC
Package Number
MTC24
Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pin Descriptions
Pin Names
Description
TTLIN, GTLPIN Clock Inputs
(LVTTL and GTLP respectively)
OEB
OEA
V
CCT
.GNDT
V
CC
GNDG
V
REF
OA0鈥揙A5
OB0鈥揙B1
Output Enable (Active LOW)
GTLP Port (LVTTL Levels)
Output Enable (Active LOW)
TTL Port (LVTTL Levels)
TTL Output Supplies
Internal Circuitry V
CC
OBn GTLP Output Grounds
Voltage Reference Input
TTL Buffered Clock Outputs
GTLP Buffered Clock Outputs
Connection Diagram
漏 2000 Fairchild Semiconductor Corporation
DS500179
www.fairchildsemi.com
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