GTLP1B153 1-Bit LVTTL/GTLP Driver/Receiver Pair
June 2001
Revised December 2001
GTLP1B153
1-Bit LVTTL/GTLP Driver/Receiver Pair
General Description
The GTLP1B153 is a 1-bit bus buffer pair with separate bit
paths, that provide LVTTL-to-GTLP and GTLP-to-LVTTL
signal level translation. High speed backplane operation is
a direct result of GTLP鈥檚 reduced output swing (
<
1V),
reduced input threshold levels and output edge rate con-
trol. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild鈥檚 GTLP has internal edge-rate control and is pro-
cess, voltage and temperature compensated. GTLP鈥檚 I/O
structure is similar to GTL and BTL but offers different out-
put levels and receiver threshold. Typical GTLP output volt-
age levels are: V
OL
=
0.5V, V
OH
=
1.5V, and V
REF
=
1V.
Features
s
Interface between LVTTL and GTLP logic levels
s
Designed with edge rate control circuitry to reduce
output noise in the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustability
s
Special PVT compensation circuitry to provide
consistent performance over variations of process,
supply voltage and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A Port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
A Port source/sink
鈭?/div>
24mA/
+
24mA
s
B Port sink
+
50mA
Ordering Code:
Order Number
GTLP1B153M
GTLP1B153MX
GTLP1B153K8X
Package Number
M08A
M08A
MAB08A
(Preliminary)
Package Description
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
8-Lead US8, 0.7mm x 3.1mm x 2.0mm
[TAPE and REEL]
Pin Descriptions
Pin Names
OEA
Description
LVTTL Bit Level Output Enable
(Active LOW for Receive)
Connection Diagrams
US8
V
CC
, GND, V
REF
Device Supplies
B
O
, B
I
A
O
/ A
I
B Port GTLP Outputs/ Inputs
A Port LVTTL Outputs/ Inputs
SOIC
漏 2001 Fairchild Semiconductor Corporation
DS500485
www.fairchildsemi.com
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