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GTLP18T612 Datasheet

  • GTLP18T612

  • 18-Bit LVTTL/GTLP Universal Bus Transceiver

  • 77.99KB

  • 9頁

  • FAIRCHILD

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GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver
May 1999
Revised September 1999
GTLP18T612
18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver
which provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct result of GTLP鈥檚 reduced output swing
(< 1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Edge Rate Control to minimize noise on the GTLP port
s
Power up/down high impedance for live insertion
s
External V
REF
pin for receiver threshold
s
BiCMOS technology for low power dissipation
s
Bushold data inputs on A Port eliminates the need for
external pull-up resistors for unused inputs
s
LVTTL compatible Driver and Control inputs
s
Flow-through architecture optimizes PCB layout
s
Open drain on GTLP to support wired-or connection
s
A-Port source/sink
鈭?4
mA/+24 mA
s
B-Port sink capability +50 mA
s
D-type flip-flop, latch and transparent data paths
Ordering Code:
Order Number
GTLP18T612MEA
GTLP18T612MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300鈥?Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
漏 1999 Fairchild Semiconductor Corporation
DS500169
www.fairchildsemi.com

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