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GTLP18T612MEAX Datasheet

  • GTLP18T612MEAX

  • BUS TRANSCEIVER|SINGLE|18-BIT|CMOS|SSOP|56PIN|PLASTIC

  • 10頁

  • ETC

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GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver
May 1999
Revised July 2002
GTLP18T612
18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver
which provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct result of GTLP鈥檚 reduced output swing
(
<
1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild鈥檚 GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
D-type flip-flop, latch and transparent data paths
s
A Port source/sink
鈭?/div>
24mA/
+
24mA
s
B Port sink
+
50mA
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
GTLP18T612G
(Note 1)(Note 2)
GTLP18T612MEA
(Note 2)
GTLP18T612MTD
(Note 2)
Package Number
BGA54A
MS56A
MTD56
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
Ordering code 鈥淕鈥?indicates Trays.
Note 2:
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
漏 2002 Fairchild Semiconductor Corporation
DS500169
www.fairchildsemi.com

GTLP18T612MEAX 產(chǎn)品屬性

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 通用總線函數(shù)

  • 74GTLP

  • 通用總線收發(fā)器

  • -

  • 18 位

  • 24mA，24mA

  • 3.15 V ~ 3.45 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-BSSOP（0.295"，7.50mm 寬）

  • 56-SSOP

  • 帶卷 (TR)

GTLP18T612MEAX相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Increase the speed of parallel backplanes 3x
  • 英文版
    8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEI...
    TI [Texas ...
  • 英文版
    CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
    FAIRCHILD
  • 英文版
    CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
    FAIRCHILD ...
  • 英文版
    17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
    FAIRCHILD
  • 英文版
    17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
    FAIRCHILD ...
  • 英文版
    17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Cl...
    FAIRCHILD
  • 英文版
    17-Bit TTL/GTLP Synchronous Bus Transceiver with Buff...
    FAIRCHILD ...
  • 英文版
    1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Fe...
    FAIRCHILD
  • 英文版
    1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port...
    FAIRCHILD ...
  • 英文版
    1-Bit LVTTL/GTLP Driver/Receiver Pair
    Fairchild
  • 英文版
    2-Bit LVTTL/GTLP Transceiver
    FAIRCHILD
  • 英文版
    2-Bit LVTTL/GTLP Transceiver
    FAIRCHILD ...
  • 英文版
    GTLP-to-TTL 1:6 Clock Driver
    FAIRCHILD
  • 英文版
    GTLP-to-TTL 1:6 Clock Driver
    FAIRCHILD ...
  • 英文版
    Low Drive GTLP-to-LVTTL 1:6 Clock Driver
    FAIRCHILD
  • 英文版
    Low Drive GTLP-to-LVTTL 1:6 Clock Driver
    FAIRCHILD ...
  • 英文版
    8-Bit LVTTL/GTLP Bus Transceiver
    FAIRCHILD
  • 英文版
    8-Bit LVTTL/GTLP Bus Transceiver
    FAIRCHILD ...
  • 英文版
    18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRAN...
    TI [Texas ...

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