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GTLP17T616MEAX Datasheet

  • GTLP17T616MEAX

  • 17-Bit Bus Transceiver

  • 10頁

  • ETC

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GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
January 2000
Revised December 2000
GTLP17T616
17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
General Description
The GTLP17T616 is a 17-bit registered bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
flow and provides a buffered GTLP (CLKOUT) clock output
from the LVTTL CLKAB. The device provides a high speed
interface between cards operating at LVTTL logic levels
and a backplane operating at GTLP logic levels. High
speed backplane operation is a direct result of GTLP鈥檚
reduced output swing (
<
1V), reduced input threshold levels
and output edge rate control. The edge rate control mini-
mizes bus settling time. GTLP is a Fairchild Semiconductor
derivative of the Gunning Transistor logic (GTL) JEDEC
standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
D-type flip-flop, latch and transparent data paths
s
A Port source/sink
鈭?/div>
24mA/
+
24mA
s
B Port sink
+
50mA
s
GTLP buffered CLKAB signal available (CLKOUT)
Ordering Code:
Order Number
GTLP17T616MEA
GTLP17T616MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
漏 2000 Fairchild Semiconductor Corporation
DS500327
www.fairchildsemi.com

GTLP17T616MEAX 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 總線收發(fā)器

  • CMOS

  • GTLP

  • 17

  • LVTTL, TTL

  • GTLP

  • 3-State

  • - 24 mA

  • 50 mA

  • 4.6 ns

  • 3.45 V

  • 3.15 V

  • + 85 C

  • SSOP-56

  • Reel

  • 17-Bit Bus Transceiver with Voltage Translation

  • - 40 C

  • SMD/SMT

  • 1

  • Non-Inverting

  • 1000

GTLP17T616MEAX相關(guān)型號(hào)PDF文件下載

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  • 英文版
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  • 英文版
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  • 英文版
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    FAIRCHILD
  • 英文版
    17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
    FAIRCHILD ...
  • 英文版
    17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Cl...
    FAIRCHILD
  • 英文版
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  • 英文版
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  • 英文版
    1-Bit LVTTL/GTLP Driver/Receiver Pair
    Fairchild
  • 英文版
    2-Bit LVTTL/GTLP Transceiver
    FAIRCHILD
  • 英文版
    2-Bit LVTTL/GTLP Transceiver
    FAIRCHILD ...
  • 英文版
    GTLP-to-TTL 1:6 Clock Driver
    FAIRCHILD
  • 英文版
    GTLP-to-TTL 1:6 Clock Driver
    FAIRCHILD ...
  • 英文版
    Low Drive GTLP-to-LVTTL 1:6 Clock Driver
    FAIRCHILD
  • 英文版
    Low Drive GTLP-to-LVTTL 1:6 Clock Driver
    FAIRCHILD ...
  • 英文版
    8-Bit LVTTL/GTLP Bus Transceiver
    FAIRCHILD
  • 英文版
    8-Bit LVTTL/GTLP Bus Transceiver
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  • 英文版
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