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GTLP16T1655 Datasheet

  • GTLP16T1655

  • 16-Bit LVTTL/GTLP Universal Bus Transceiver

  • 14頁

  • FAIRCHILD

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GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver
August 1998
Revised April 2000
GTLP16T1655
16-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP16T1655 is a 16-bit universal bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface
between cards operating at LVTTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP鈥檚 reduced output
swing (<1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver Logic (GTL) JEDEC standard
JESD8-3.
Fairchild鈥檚 GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Variable Edge Rate Control pin to select desired edge
rate on the GTLP backplane (V
ERC
)
s
Partitioned as two 8-Bit transceivers with individual latch
timing and output control but with a common clock.
s
Power up/down high impedance for live insertion.
s
External pin to pre-condition I/O capacitance to high
state
s
Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs
s
LVTTL compatible driver and control inputs
s
Flow through pinout optimizes PCB layout
s
Open drain on GTLP to support wired-or connection
s
A Port source/sink
鈭?4
mA/+24 mA
s
B Port sink
+100mA
s
D-type flip-flop, latch and transparent data paths
s
鈭?0擄C
to 85擄C Temperature capability
s
Available in TSSOP
Ordering Code:
Order Number
GTLP16T1655MTD
Package Number
MTD64
Package Description
64-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
漏 2000 Fairchild Semiconductor Corporation
DS500172
www.fairchildsemi.com

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