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GTLP16T1655MTDX Datasheet

  • GTLP16T1655MTDX

  • Dual 8-bit Bus Transceiver

  • 13頁

  • ETC

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GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls
August 1998
Revised December 2000
GTLP16T1655
16-Bit LVTTL/GTLP Universal Bus Transceiver
with High Drive GTLP and Individual Byte Controls
General Description
The GTLP16T1655 is a 16-bit universal bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface
between cards operating at LVTTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP鈥檚 reduced output
swing (
<
1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver Logic (GTL) JEDEC standard
JESD8-3.
Fairchild鈥檚 GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Variable edge rate control pin to select desired edge rate
on the GTLP backplane (V
ERC
)
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
D-type flip-flop, latch and transparent data paths
s
A Port source/sink
鈭?/div>
24mA/
+
24mA
s
B Port sink
+
100mA
s
Partitioned as two 8-bit transceivers with individual latch
timing and output control but with a common clock
s
External pin to pre-condition I/O capacitance to high
state (V
CCBIAS
)
Ordering Code:
Order Number
GTLP16T1655MTD
Package Number
MTD64
Package Description
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
漏 2000 Fairchild Semiconductor Corporation
DS500172
www.fairchildsemi.com

GTLP16T1655MTDX 產(chǎn)品屬性

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 通用總線函數(shù)

  • 74GTLP

  • 通用總線收發(fā)器

  • -

  • 16 位

  • 24mA，24mA

  • 3 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 64-TSSOP

  • 64-TSSOP

  • 帶卷 (TR)

GTLP16T1655MTDX相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Increase the speed of parallel backplanes 3x
  • 英文版
    8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEI...
    TI [Texas ...
  • 英文版
    CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
    FAIRCHILD
  • 英文版
    CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
    FAIRCHILD ...
  • 英文版
    17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
    FAIRCHILD
  • 英文版
    17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
    FAIRCHILD ...
  • 英文版
    17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Cl...
    FAIRCHILD
  • 英文版
    17-Bit TTL/GTLP Synchronous Bus Transceiver with Buff...
    FAIRCHILD ...
  • 英文版
    1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Fe...
    FAIRCHILD
  • 英文版
    1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port...
    FAIRCHILD ...
  • 英文版
    1-Bit LVTTL/GTLP Driver/Receiver Pair
    Fairchild
  • 英文版
    2-Bit LVTTL/GTLP Transceiver
    FAIRCHILD
  • 英文版
    2-Bit LVTTL/GTLP Transceiver
    FAIRCHILD ...
  • 英文版
    GTLP-to-TTL 1:6 Clock Driver
    FAIRCHILD
  • 英文版
    GTLP-to-TTL 1:6 Clock Driver
    FAIRCHILD ...
  • 英文版
    Low Drive GTLP-to-LVTTL 1:6 Clock Driver
    FAIRCHILD
  • 英文版
    Low Drive GTLP-to-LVTTL 1:6 Clock Driver
    FAIRCHILD ...
  • 英文版
    8-Bit LVTTL/GTLP Bus Transceiver
    FAIRCHILD
  • 英文版
    8-Bit LVTTL/GTLP Bus Transceiver
    FAIRCHILD ...
  • 英文版
    18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRAN...
    TI [Texas ...

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