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GTLP16612MEA Datasheet

  • GTLP16612MEA

  • CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

  • 9頁

  • FAIRCHILD

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GTLP16612 CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
March 1995
Revised October 1998
GTLP16612
CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
General Description
The GTLP16612 is an 18-bit universal bus transceiver
which provides TTL to GTLP signal level translation. The
device is designed to provide a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP鈥檚 reduced output
swing (<1V), reduced input threshold levels and output
edge rate control which minimizes signal settling times.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transceiver Logic (GTL) JEDEC standard JESD8-3.
Fairchild鈥檚 GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different driver
output levels and receiver threshold. GTLP output low volt-
age is typically less than 0.5V, the output high is 1.5V and
the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and TTL logic
levels
s
Designed with Edge Rate Control Circuit to reduce
output noise
s
V
REF
pin provides external supply reference voltage for
receiver threshold
s
Submicron Core CMOS technology for low power
dissipation
s
Special PVT Compensation circuitry to provide consis-
tent performance over variations of process, supply
voltage and temperature
s
5V tolerant inputs and outputs on A-Port
s
Bus-Hold data inputs on A-Port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down high impedance
s
TTL compatible Driver and Control inputs
s
A-Port outputs source/sink
鈭?2
mA/+32 mA
s
Flow-through architecture optimizes PCB layout
s
Open drain on GTLP to support wired-or connection
Ordering Code:
Order Number
GTLP16612MEA
GTLP16612MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300鈥?Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
漏 1998 Fairchild Semiconductor Corporation
DS012390.prf
www.fairchildsemi.com

GTLP16612MEA 產(chǎn)品屬性

  • 25

  • 集成電路 (IC)

  • 邏輯 - 通用總線函數(shù)

  • 74GTLP

  • 通用總線收發(fā)器

  • -

  • 18 位

  • 32mA，32mA

  • 3.15 V ~ 3.45 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-BSSOP（0.295"，7.50mm 寬）

  • 56-SSOP

  • 管件

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