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GTLP16612AA Datasheet

  • GTLP16612AA

  • 18-Bit Bus Transceiver

  • 8頁

  • ETC

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CE
1D
CI
CLK
V
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1
2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
GTLP16612A
CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
Product Description
Pericom Semiconductor聮s GTLP series of logic circuits are produced
using the Company聮s advanced 0.5 micron CMOS technology,
achieving industry leading performance.
Features
聲 Bidirectional interface between GTLP and TTL
logic levels
聲 Designed with Edge Rate Control Circuit to
reduce output noise
聲 V
REF
pin provides external supply reference voltage
for receiver threshold
聲 5V tolerant inputs and outputs on A-Port
聲 Increased B-Port Drive, 50mA
聲 Bus-Hold data inputs on A-Port to eliminate the need for
pull-up resistors for unused inputs
聲 Power up/down high impedance
聲 TTL compatible Driver and Control inputs
聲 A-Port Balanced Drive: 聳32mA/+32mA
聲 Flow-through architecture
聲 Open drain on GTLP to support wired-or connection
聲 Package:
聴 56-pin 240 Mil Wide Plastic TSSOP (A)
The GTLP16612A 18-bit universal transceiver provides TTL to GTLP
signal level translation. The device is designed to provide high-
speed interface between cards operating at TTL logic levels and a
back plane operating at GTLP logic levels. High-speed back plane
operation is a direct result of GTLP聮s reduced output swing (<1V),
reduced input threshold levels, and output edge-rate control which
minimizes signal settling times. Its function is similar to BTL or GTL
but with modified driver output levels and receiver threshold. GTLP
output low voltage is typically less than 0.5V, the output high is 1.5V,
and the receiver threshold is 1.0V.
Pin Configuration
OEAB
LEAB
A1
GND
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
CEAB
CLKAB
B
1
GND
B2
B3
V
CCQ
(5.0V)
Logic Block Diagram
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
1
56
55
2
28
30
29
27
CE
1D
CI
CLK
1 of 18 Channels
V
CC
(3.3V)
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
B18
CLKBA
CEBA
56-Pin
A,V
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A1 3
GTLP
54
B1
A15
V
CC
(3.3V)
A16
A17
GND
A18
OEBA
LEBA
V
1 of 18 Channels
1
PS8431
09/24/99

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