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GS9032-CTM Datasheet

  • GS9032-CTM

  • SMPTE

  • 10頁(yè)

  • ETC

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GS9032
Digital Video Serializer
DATA SHEET
FEATURES
鈥?SMPTE 259M and 540Mb/s compliant
鈥?serializes 8-bit or 10-bit data
鈥?autostandard, adjustment free operation
鈥?minimal external components (no loop filter
components required)
鈥?isolated, quad output, adjustable cable driver
鈥?power saving secondary cable driver disable
鈥?3.3V and 5.0V CMOS/TTL compatible inputs
鈥?lock detect indication
鈥?SMPTE scramble and NRZI coding bypass option
鈥?EDH support with GS9001, GS9021 or EDH FPGA code
APPLICATION
SMPTE 259M and 540Mb/s parallel to serial interfaces for
video cameras, VTRs, and signal generators; generic
parallel to serial conversion.
DESCRIPTION
The GS9032 encodes and serializes SMPTE 125M and
244M bit parallel digital video signals, and other 8-bit or
10-bit parallel formats. This device performs sync
detection, parallel to serial conversion, data scrambling
9
4
(using the X + X + 1 algorithm), 10x parallel clock
multiplication and conversion of NRZ to NRZI serial data.
The GS9032 features auto standard and adjustment free
operation for data rates to 540Mb/s with a single VCO
resistor. Other features include a lock detect output, NRZI
encoding, SMPTE scrambler bypass, a sync detect disable,
and an isolated quad output cable driver suitable for driving
75鈩?loads. The complementary cable driving output swings
can be adjusted independently or the secondary differential
cable driver can be powered down.
The GS9032 requires a single +5 volt or -5 volt supply and
typically consumes 675mW of power while driving four 75鈩?/div>
loads.
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
GS9032
GS9032 - CVM
GS9032 - CTM
44 pin TQFP
44 pin TQFP Tape
0擄C to 70擄C
0擄C to 70擄C
SYNC DETECT DISABLE (SYNC DIS)
RESET
BYPASS
10
DATA
IN
(PD0-PD9)
10
INPUT
LATCH
SYNC
DETECT
2
10
PARALLEL
to SERIAL
CONVERTER
&
NRZ to NRZI
SDO0
SDO0
SERIAL
DIGITAL
OUTPUTS
SDO1
SDO1
S
CLK
/10
S
CLK
P
LOAD
SDO1
ENABLE
PLL
MUTE
LOCK
DETECT
(LOCK DET)
R
VCO+
R
VCO-
8
SMPTE
SCRAMBLER
RESET
BYPASS
PARALLEL CLOCK
INPUT (PCLKIN)
AUTO/MANUAL SELECT
(AUTO/MAN)
LOOP BANDWIDTH
CONTROL (LBWC)
DATA RATE SELECT
SS[2:0]
3
BLOCK DIAGRAM
Revision Date: June 2001
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Document No. 521 - 96 - 06

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