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GS9020A Datasheet

  • GS9020A

  • Deserializer with EDH for SDI at 143-540Mb/s and DVB-ASI.

  • 30頁

  • ETC

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GS9020A
Serial Digital Video Input Processor
DATA SHEET
FEATURES
鈥?fully compatible with SMPTE 259M
鈥?drop-in replacement for the GS9020
鈥?auto-standard operation to 540MHz
鈥?embedded EDH and data processing core
鈥?selectable loop through or re-serialized EDH-processed
serial output
鈥?noise immune HVF timing signal outputs
鈥?configurable FIFO reset pulse for clearing downstream
FIFOs
鈥?ANC header and TRS-ID correction for all standards
鈥?user controlled output blanking
鈥?ITU-R-601 output clipping for active picture area
鈥?ancillary data indication
鈥?low system power
鈥?selectable I虜C interface or 8-bit parallel port for access to
EDH flags and device configuration bits
鈥?EDH flags also available on dedicated pins
鈥?seamless flag mapping to GS9021 EDH coprocessor
鈥?80 pin LQFP
APPLICATIONS
SMPTE 259M serial digital receiver for composite and
component standards including 4:4:4:4 at 540Mb/s with
EDH processing; Noise immune digital sync and timing
generation; Cost effective EDH insertion and checking for
serial routing and distribution applications.
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
DESCRIPTION
The GS9020A is specifically designed to deserialize SMPTE
259M serial digital signals. The inclusion of Error Detection
and Handling (EDH) ensures the integrity of the data being
received from the serial digital interface (SDI). Internal 75鈩?/div>
termination resistors allow INTERLINX鈩?seamless
connection with the GS9035A Reclocker or the GS9025A
Receiver, thus providing a complete high performance,
digital video input processor with EDH, digital sync signal
generation, and other system features.
The GS9020A also includes a parallel to serial converter
and NRZI scrambler to provide re-serialized, EDH
compliant data output. The EDH core implements EDH
insertion and extraction according to SMPTE RP-165. This
core also generates noise immune timing signals such as
horizontal sync, vertical blanking, field ID and ancillary data
identification. It also provides many system features such
as a FIFO reset pulse (which can be programmed to
coincide with either EAV or SAV), TRS-ID and ANC header
correction, user controlled output blanking and ITU-R-601
output clipping. The GS9020A has an I虜C (Inter-Integrated
Circuit, I虜C is a registered Trademark of Philips) serial
interface bus and an 8-bit parallel port for external access
to all error flags and device configuration bits.
GS9020A
GS9020ACFV
GS9020ACTV
80 pin LQFP Tray
80 pin LQFP Tape
0擄C to 70擄C
0擄C to 70擄C
SDOMODE
PARALLEL TO
SERIAL
CONVERTER
WITH SCRAMBLER
DESCRAMBLER
BUF
SDI
SERIAL TO
PARALLEL
CONVERTER
10
SYNC
DETECTOR
EDH
AND DATA
PROCESSING
CORE
FRAMED
DATA [9:0]
10
SDO
BUF
SDO
0
1
SDI
DOUT[9:0]
FIFO_RESET
5
HVF
CLIP_TRS
ANC_CHKSM
SCI
BUF
SCI
SCRAMBLER
PRESCALER
PCLK OUT
ALIGNING
CONTROL
UNIT
4
RESET
7
STANDARDS
INDICATOR
HOSTIF
TRS_ERR
DEDICATED
FLAG PORT
PCLKOUT
BLOCK DIAGRAM
Revision Date: March 2002
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Document No. 19922 - 2

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