鈩?/div>
GS9002
Serial Digital Encoder
DATA SHEET
FEATURES
鈥?fully compatible with SMPTE-259M serial digital
standard
鈥?supports up to four serial bit rates to 400 Mb/s
鈥?accepts 8 bit and 10 bit TTL and CMOS
compatible parallel data inputs
鈥?X + X + 1 scrambler, NRZI converter and sync
detector may be disabled for transparent data
transmission
鈥?pseudo-ECL serial data and clock outputs
鈥?single +5 or -5 volt supply
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DEVICE DESCRIPTION
The GS9002 is a monolithic bipolar integrated circuit designed
to serialize SMPTE 125M and SMPTE 244M bit parallel digital
signals as well as other 8 or 10 bit parallel formats. This device
performs the functions of sync detection, parallel to serial
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4
conversion, data scrambling (using the X + X +1 algorithm),
10x parallel clock multiplication and conversion of NRZ to
NRZI serial data. It supports any of four selectable serial data
rates from 100 Mb/s to over 360 Mb/s. The data rates are set
by resistors and are selected by an on-board 2:4 decoder
having two TTL level input address lines.
鈥?713 mW typical power dissipation (including ECL
pull-down loads).
鈥?44 pin PLCC packaging
APPLICATIONS
鈥?4茠
SC
, 4:2:2 and 360 Mb/s serial digital interfaces for
Video cameras, VTRs, Signal generators
ORDERING INFORMATION
Part Number
GS9002 - CPM
SYNC DETECT
DISABLE
PARALLEL DATA
IN (10 BITS)
D
E
D S
N N
E G
M SI
M E
O D
C
E W
R E
T N
O R
N O
F
Other features such as a sync detector output, a sync detector
disable input, and a lock detect output are also provided. The
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X + X + 1 scrambler and NRZ to NRZI converter may be
bypassed to allow the output of the parallel to serial converter
to be directly routed to the output drivers.
The GS9002 provides pseudo-ECL outputs for the serial data
and serial clock as well as a single-ended pseudo-ECL output
of the regenerated parallel clock.
The GS9002 directly interfaces with cable drivers GS9007,
GS9008 and GS9009. The device requires a single +5 volt or
-5 volt supply and typically consumes 713 mW of power while
driving 100
鈩?/div>
loads. The 44 pin PLCC packaging assures a
small footprint for the complete encoder function.
Package Type
44 Pin PLCC
Temperature Range
0擄 to 70擄C
SCRAMBLER/
SERIALIZER
SELECT
26
6
3
SYNC DETECT
SERIAL DATA
2:1 MUX
38
7-16
INPUT
LATCH
SYNC
DETECT
39
P/S
CONVERTER
SERIAL DATA
SCRAMBLER
NRZ
NRZI
42
SERIAL CLOCK
PLD
SCLK
43
SERIAL CLOCK
LOCK
DETECT
20
LOCK DETECT
PCLK IN
17
PHASE
FREQUENCY
DETECT
CHARGE
PUMP
VCO
29
REGULATOR CAP
LOOP FILTER
PCLK OUT
22
19
DIV BY 10
GENERATOR
DATA RATE
SWITCH
36
35
DRS0
DRS1
34
33
32
31
RVC00
RVC01
RVC02
RVC03
GS9002
Patent No.5,357,220
FUNCTIONAL BLOCK DIAGRAM
Revision Date: March 2001
Document No. 520 - 27 - 08
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan Corporation C-101 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168-0081, Japan
tel. (03) 3334-7700
fax (03) 3247-8839
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