鈥?/div>
fully compatible with SMPTE 259M
decodes 8 and 10 bit serial digital signals for data
rates to 300 Mb/s
pin and function compatible with GS9000B and
GS9000
250 mW power dissipation at 270 MHz clock rates
incorporates an automatic standards selection
function with the GS9005A Receiver or GS9015A
Reclocker
operates from single +5 or -5 volt supply
enables an adjustment-free Deserializer system
when used with GS9010A and GS9005A or
GS9015A
28 pin PLCC packaging
DEVICE DESCRIPTION
GS9000S
The GS9000S is a CMOS integrated circuit specifically
designed to deserialize SMPTE 259M serial digital signals
at data rates to 300Mbps.
The device incorporates a descrambler, serial to parallel
convertor, sync processing unit, sync warning unit and
automatic standards select circuitry.
NOT RECOMMENDED FOR NEW DESIGNS
鈥?/div>
鈥?/div>
Differential pseudo-ECL inputs for both serial clock and
data are internally level shifted to CMOS levels. Digital
outputs such as parallel data, parallel clock, HSYNC, Sync
Warning and Standard Select are all TTL compatible.
The GS9000S is designed to directly interface with the
GS9005A Reclocking Receiver to form a complete
SMPTE-serial-in to CMOS level parallel-out deserializer.
The GS9000S may also be used with the GS9010A and the
GS9005A to form an adjustment-free receiving system
which automatically adapts to all serial digital data rates.
The GS9015A can replace the GS9005A in GS9000S
applications where cable equalization is not required.
The GS9000S is packaged in a 28 pin PLCC and operates
from a single 5 volt,
鹵
5% power supply.
鈥?/div>
APPLICATIONS
鈥?/div>
鈥?/div>
4茠
SC
and 270 Mb/s , 4:2:2 serial digital interfaces
Automatic standards select controller for serial routing
and distribution applications using GS9005A Receiver
or GS9015A Reclocker
GS9000S
SERIAL DATA IN
SERIAL DATA IN
5
6
LEVEL
SHIFT
DESCRAMBLER
30 - BIT
SHIFT REG
SP
PARALLEL DATA
OUT (10 BITS)
SERIAL CLOCK IN
SERIAL CLOCK IN
7
8
LEVEL
SHIFT
ICLK
SYNC DETECT
(3FF 000 000 HEX)
Sync
Word
Boundary
PARALLEL
TIMING
GENERATOR
PARALLEL CLOCK
OUT
SYNC CORRECTION
ENABLE
14
SYNC CORRECTION
Sync Error
HSYNC OUTPUT
SYNC WARNING
CONTROL
15
SYNC WARNING
(Schmitt Trigger
Comparator)
AUTO STANDARD SELECT
STANDARDS SELECT
CONTROL
11
OSC
2 BIT
COUNTER
Hsync Reset
SS0
SS1
SYNC WARNING
FLAG
Revision Date: December 1999
FUNCTIONAL BLOCK DIAGRAM
Document No. 521 - 80 - 02
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum
Electronic-Library Service CopyRight 2003
Powered by ICminer.com
Japan Corporation A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan
tel. (03) 3334-7700
fax (03) 3247-8839
GS9000SCTJ相關(guān)型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
英文版
ETC
-
英文版
Serial Digital Decoder
GENNUM [Ge...
-
英文版
EDH COPROCESSOR
ETC
-
英文版
EDH COPROCESSOR
-
英文版
ETC
-
英文版
GENLINXTM GS9002 Serial Digital Encoder
GENNUM [Ge...
-
英文版
ETC
-
英文版
ETC
-
英文版
Quad Cable Driver - 4 fixed O/P level
ETC
-
英文版
Cable Driver with Two Adjustable Outputs
ETC
-
英文版
Cable Driver with Two Adjustable Outputs
ETC [ETC]
-
英文版
GS9009 CABLE DRIVER WITH FOUR ADJUSTABLE OUTPUTS
ETC
-
英文版
GS9009 CABLE DRIVER WITH FOUR ADJUSTABLE OUTPUTS
ETC [ETC]
-
英文版
ETC
-
英文版
TRANSISTOR | BJT | PNP | 20V V(BR)CEO | 500MA I(C) | TO-226A...
ETC
-
英文版
TRANSISTOR | BJT | NPN | 20V V(BR)CEO | 500MA I(C) | TO-226A...
ETC
-
英文版
Serial Digital Video Input Processor
ETC
-
英文版
Serial Digital Video Input Processor
ETC [ETC]
-
英文版
EDH Coprocessor
ETC
-
英文版
EDH Coprocessor
1
2
3
4
5
6
7
8
