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GS9000D Datasheet

  • GS9000D

  • 270Mb/s Deserializer for use with GS7025. GS9025A or GS9035A...

  • 9頁

  • ETC

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GS9000D
Serial Digital Decoder
DATA SHEET
FEATURES
鈥?fully compatible with SMPTE 259M-ABC
鈥?decodes 8 and 10 bit serial digital signals for data rates to
270Mb/s
鈥?recommended alternative to GS9000C for use when
interfacing directly to GS7025, GS9025A or GS9035A
鈥?incorporates automatic standards selection
鈥?325mW power dissipation at 270MHz clock rate
鈥?operates from single +5 or -5 volt supply
鈥?28 pin PLCC packaging
APPLICATIONS
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4茠
SC
and 4:2:2 serial digital interfaces
Automatic standards select controller for serial routing
and distribution applications
Differential pseudo-ECL inputs for both serial clock and
data are internally level shifted to CMOS levels. Digital
outputs such as parallel data, parallel clock, HSYNC, Sync
Warning and Standard Select are all TTL compatible.
The GS9000D is packaged in a 28 pin PLCC and operates
from a single 5 volt, 鹵5% power supply.
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
DEVICE DESCRIPTION
The GS9000D is a CMOS integrated circuit specifically
designed to deserialize SMPTE 259M serial digital signals
at data rates up to 270Mb/s. The GS9000D is a pin and
functional equivalent to the GS9000C, with the exception of
SDI input levels which are compatible for direct interfacing
to the GS7025, GS9025A and GS9035A.
The device incorporates a descrambler, serial to parallel
convertor, sync processing unit, sync warning unit and
automatic standards select circuitry.
GS9000D
GS9000DCPJ
GS9000DCTJ
28 Pin PLCC
28 Pin PLCC Tape
0擄C to 70擄C
0擄C to 70擄C
GS9000D
SERIAL DATA IN
SERIAL DATA IN
LEVEL
SHIFT
30 - BIT
SHIFT REG
PARALLEL DATA
OUT (10 BITS)
DESCRAMBLER
SP
SERIAL CLOCK IN
SERIAL CLOCK IN
LEVEL
SHIFT
SCLK
SYNC DETECT
(3FF 000 000 HEX)
Sync
Word
Boundary
PARALLEL
TIMING
GENERATOR
PARALLEL CLOCK
OUT
SYNC CORRECTION
ENABLE
SYNC CORRECTION
Sync Error
HSYNC OUTPUT
SYNC WARNING
CONTROL
SYNC WARNING
(Schmitt Trigger
Comparator)
AUTO STANDARD SELECT
SYNC WARNING
FLAG
STANDARDS SELECT
CONTROL
OSC
2 BIT
COUNTER
Hsync Reset
SS0
SS1
FUNCTIONAL BLOCK DIAGRAM
Revision Date: February 2002
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Document No. 18784 - 2

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