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GS8342S09GE-167I Datasheet

  • GS8342S09GE-167I

  • 36Mb Burst of 2 DDR SigmaSIO-II SRAM

  • 39頁(yè)

  • GSI

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Preliminary
GS8342S08/09/18/36E-333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
Features
鈥?Simultaneous Read and Write SigmaSIO鈩?Interface
鈥?JEDEC-standard pinout and package
鈥?Dual Double Data Rate interface
鈥?Byte Write controls sampled at data-in time
鈥?DLL circuitry for wide output data valid window and future
frequency scaling
鈥?Burst of 2 Read and Write
鈥?1.8 V +100/鈥?00 mV core power supply
鈥?1.5 V or 1.8 V HSTL Interface
鈥?Pipelined read operation
鈥?Fully coherent read and write pipelines
鈥?ZQ mode pin for programmable output drive strength
鈥?IEEE 1149.1 JTAG-compliant Boundary Scan
鈥?165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
鈥?RoHS-compliant 165-bump BGA package available
鈥?Pin-compatible with future 72Mb and 144Mb devices
36Mb Burst of 2
DDR SigmaSIO-II SRAM
167 MHz鈥?33 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
SigmaRAM鈩?Family Overview
GS8342S08/09/18/36 are built in compliance with the
SigmaSIO-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It
employs dual input register clock inputs, K and K. The device
also allows the user to manipulate the output register clock
input quasi independently with dual output register clock
inputs, C and C. If the C clocks are tied high, the K clocks are
routed internally to fire the output registers instead. Each Burst
of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,
CQ and CQ, which are synchronized with read data output.
When used in a source synchronous clocking scheme, the Echo
Clock outputs can be used to fire input registers at the data鈥檚
destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 2M x 18 has a 1M
addressable index).
Parameter Synopsis
- 333
tKHKH
tKHQV
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.02 8/2005
1/39
漏 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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