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GS1561* Datasheet

  • GS1561*

  • Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without...

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  • 54頁

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GS1561
HD-LINX
鈩?/div>
II
Multi-Rate Deserializer
PRELIMINARY DATA SHEET
KEY FEATURES
鈥?SMPTE 292M and SMPTE 259M-C compliant
descrambling and NRZI
鈫?/div>
NRZ decoding (with
bypass)
鈥?DVB-ASI sync word detection and 8b/10b decoding
鈥?auto-configuration for HD-SDI, SD-SDI and DVB-ASI
鈥?dual serial digital input buffers with 2 x 1 mux
鈥?integrated serial digital signal termination
鈥?integrated reclocker
鈥?automatic or manual rate selection / indication
(HD/SD)
鈥?descrambler bypass option
鈥?adjustable loop bandwidth
鈥?user selectable additional processing features
including:
- CRC, TRS, ANC data checksum, line number and
EDH CRC error detection and correction
- programmable ANC data detection
- illegal code remapping
鈥?internal flywheel for noise immune H, V, F extraction
鈥?FIFO load Pulse
鈥?20-bit / 10-bit CMOS parallel output data bus
鈥?148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel digital
output
鈥?automatic standards detection and indication
鈥?1.8V core power supply and 3.3V charge pump power
supply
鈥?3.3V digital I/O supply
鈥?JTAG test interface
鈥?small footprint compatible with GS1560A, GS1532,
GS9060 and GS9062
APPLICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
SMPTE 292M Serial Digital Interfaces
SMPTE 259M-C Serial Digital Interfaces
DVB-ASI Serial Digital Interfaces
DESCRIPTION
The GS1561 is a reclocking deserializer. When used in
conjunction with the GS1524 Automatic Cable Equalizer
and the GO1525 Voltage Controlled Oscillator, a receive
solution can be realized for HD-SDI, SD-SDI and DVB-ASI
applications.
In addition to reclocking and deserializing the input data
stream, the GS1561 performs NRZI-to-NRZ decoding,
descrambling as per SMPTE 292M/259M-C, and word
alignment when operating in SMPTE mode. When operating
in DVB-ASI mode, the device will word align the data to
K28.5 sync characters and 8b/10b decode the received
stream.
Two serial digital input buffers are provided with a 2x1
multiplexer to allow the device to select from one of two
serial digital input signals.
The integrated reclocker features a very wide Input Jitter
Tolerance of 鹵0.3 UI (total 0.6 UI), a rapid asynchronous
lock time, and full compliance with DVB-ASI data streams.
The GS1561 also includes a range of data processing
functions such as error detection and correction, automatic
standards detection, and EDH support. The device can
also detect and extract SMPTE 325M payload identifier
packets and independently identify the received video
standard. This information is read from internal registers via
the host interface port.
Line-based CRC errors, line number errors, TRS errors,
EDH CRC errors and ancillary data checksum errors can all
be detected. A single 鈥楧ATA_ERROR鈥?pin is provided which
is a logical 'OR'ing of all detectable errors. Individual error
status is stored in internal 鈥楨RROR_STATUS鈥?registers.
Finally, the device can correct detected errors and insert
new TRS ID words, line-based CRC words, ancillary data
checksum words, EDH CRC words, and line numbers.
Illegal code re-mapping is also available. All processing
function may be individually enabled or disabled via host
interface control.
GS1561
Revision Date: July 2003
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Document No. 22048 - 1

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