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GMM2649233ETG Datasheet

  • GMM2649233ETG

  • 16Mx64|3.3V|P/S|x8|SDR SDRAM - Unbuffered DIMM 128MB

  • 126.85KB

  • 12頁

  • ETC

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16Mx72 bits
PC100/PC133 SDRAM Registered DIMM
based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
GMM27316230ETG
Description
The GMM27316230ETG is a 16M x 72bits
Synchronous Dynamic RAM MODULE
which is assembled 18 pieces of 16M x 4bits
Synchronous DRAMs in 54 pin TSOP II, 2
pieces of 16 bits Register in 48 pin TSSOP,
one clock distribution PLL in 24 pin SOP and
one 2048 bit EEPROM in 8 pin TSSOP
package mounted on a 168 pin printed circuit
board with decoupling capacitors. The
GMM27316230ETG is optimized for
application to the systems which are required
high density and large capacity such as main
memory of the computers and an image
memory systems, and to the others which are
requested compact size.
The GMM27316230ETG provides common
data inputs and outputs.
GMM27316230ETG
(Double Side)
Features
* PC133/PC100/PC66 Compatible
-7(143MHz)/-75(133MHz)/-8(125MHz)
-7K(PC100,2-2-2)/-7J(PC100,3-2-2)
* 3.3V
鹵
0.3V Power supply
* Maximum Clock frequency
100/125/133/143 MHz
* LVTTL Interface
* Burst read/write operation and burst read/
single write operation capability
* Programmable burst length ;
1, 2, 4, 8, Full page
* Programmable burst sequence
Sequential / Interleave
* Full Page burst length capability
Sequential burst
Burst stop capability
* Programmable CAS Latency ; 2, 3
* CKE power down mode
* Input / Output data masking
* 4096 Refresh Cycles / 64ms
* Auto refresh / Self refresh Capability
* Serial Presence Detect with EEPROM
Pin Name
CK0, 1, 2, 3
CKE0
S0, 2
RAS
CAS
WE
A0 ~ A11
BA0,1
REGE
DQ0 ~ 63
CB0 ~ 7
DQMB0 ~ 7
V
CC
V
SS
NC
V
REF
SDA
SCL
SA0 ~ 2
WP
DU
Clock input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address input
Bank Address input
Register Enable
Data input / output
Check Bits
Data input / output Mask
Power for internal circuit
Ground for internal circuit
No Connect
Power Supply for Reference
Serial Data input/ output
Serial Clock
Address in EEPROM
Write Protect for SPD
Don't Use
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Apr.01
-1-

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