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GD16524-100BA Datasheet

  • GD16524-100BA

  • CLOCK/DATA RECOVERY|QFP|100PIN|PLASTIC

  • 132.09KB

  • 13頁(yè)

  • ETC

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an Intel company
2.5 Gbit/s
Clock and Data
Recovery and
1:16 DeMUX
GD16524
Features
The CDR contains all circuits needed for
reliable acquisition and lock of the VCO
phase to the incoming data-stream.
The electrical input sensitivity is better
than 8 mV (BER <10
-10
).
The device exceeds all ITU-T and
Bellcore IEEE jitter requirements when
used with the recommended loop filter,
according to Figure 3 (jitter tolerance,
-transfer and -generation).
The output clock (2.488 GHz when
STM-16 data input is selected) is main-
tained within 500 ppm tolerance of the
reference frequency in the absence of
data.
The integrated 1:16 de-multiplexer with
differential LVPECL outputs provides a
simple interface to system ASICs.
The GD16524 is available in a 100 pin
TQFP package (14 脳 14 mm) with heat
slug on bottom surface.
l
General Description
The GD16524 is a high performance
monolithic integrated multi-rate
Clock
and Data Recovery
(CDR) device appli-
cable for optical communication systems
including:
u
SDH STM-16 / 4 / 1
u
SONET OC-48 / 12 / 3
u
Gigabit Ethernet
The GD16524 features:
u
Limiting input amplifier.
u
Analogue peak level detection circuit.
u
Digital Loss Of Signal (LOS) monitor
circuit with four selectable threshold
settings.
u
Consecutive Identical Binary Digit
alarm output.
u
1:16 de-multiplexer.
GD16524 can be switched 鈥渙n-the-fly鈥?to
and from 2.488 Gbit/s, 1.244 Gbit/s,
622.08 Mbit/s, and 155.52 Mbit/s.
GD16524 also supports up to 7% over-
head, allowing for 2.66 Gbit/s data
transfer.
The device also features an additional
high-speed data input for serial loop-back
diagnostic tests.
DEC_ADJ SD_SEL
TCK
VCTL
BRS0
BRS1
SELTCK
Exceeds ITU-T and Bellcore require-
ments of Jitter Transfer, Generation
and Tolerance.
Integrated Limiting amplifier.
On-the-fly multi-bit-rate operation
7% overhead data rate capability.
Digital LOS monitor and alarm output.
Bit Consecutive Detect output.
Multi-rate data input.
Differential CML data input with
internal 50
W
load termination.
Integrated 1:16 DeMUX with LVPECL
outputs.
Control inputs are LVTTL.
Reference clock selectable:
鈥?155.52 MHz
鈥?38.88 MHz
High-speed serial loop-back input.
Single supply operation: +3.3 V
Power dissipation: 800 mW (typ.)
Available in a 100 pin TQFP package
(14 脳 14 mm) with heat slug on
bottom surface.
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MON
MON_REF
SDIP
DIREF
SDIN
DIREFN
Peak
Detect
Divider
VCO
PCOP
PCON
DO0
DON0
l
MUX
Limiting
Amplifier
B.B
Phase
Detector
DO15
DON15
VCC
VCCL
VCCO
VCCP
VCCV
BC_DET
LOCK_DET
LOCK
LOS_DET
Applications
l
SLBIP
SLBIN
Amplifier
BER
Lock
Detect
Continuous
Bit
Detector
SBER0
SBER1
/4
RCIP
RCIN
MUX
Phase
Frequency
Detect
Clock and Data Recovery for optical
communication systems including:
鈥?SDH STM-16
鈥?SONET OC-48
鈥?Gigabit Ethernet
VBB
PCTL
VEE
VEEL
VEEP
VEEV
CDR_SEL
REF_SEL
Data Sheet Rev.: 26

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